In recent years, A/D converters are broadly utilized in various fields. More specifically, a successive approximation A/D converter and a delta-sigma A/D converter are known as A/D converters with relatively high resolution. Such A/D converters include a switched-capacitor circuit, for example, and are widely used in the form of CMOS (Complementary Metal Oxide Semiconductor) integrated circuit.
As performance indexes of an A/D converter, there are linearity, an offset, and a gain error, for example. However, the advantage in the conversion characteristic of an A/D converter is largely under the control of a matching, the voltage dependence or the like of a capacitive element in many cases. Therefore, in order to realize an A/D converter with high conversion accuracy, it is preferred to apply capacitive elements with good characteristics.
Such a capacitive element with good characteristics is not limited to be applied to an A/D converter, but, for example, it may be broadly applied also to various electronic circuits including a circuit for measuring instruments.
[About Successive Approximation A/D Converter]
First, a successive approximation A/D converter will be illustrated. A successive approximation A/D converter includes an internal D/A converter (Digital-to-Analog Converter: capacitor DAC), a comparator, and a digital circuit for a successive approximation control.
The successive approximation A/D converter obtains an A/D conversion result by sampling an input analog voltage, comparing the input analog voltage with an output voltage of the capacitor DAC, and searching an output of the capacitor DAC where the two voltages match most closely.
The differential nonlinearity (DNL) of the successive approximation A/D converter is decided according to the matching of the capacitive elements included in the capacitor DAC. Then, when the matching of the capacitive elements is inferior, a code loss, which lacks a part of staircase-shaped transfer characteristic, occurs.
Moreover, the integral nonlinearity (INL) of the successive approximation A/D converter is decided according to the voltage dependence of the capacitive elements included in the capacitor DAC. When the capacitive element includes the voltage dependence, A/D conversion characteristics become nonlinear since a capacitance value changes with voltage across the capacitive element, and this may be a cause of deformation.
Hitherto, self-calibration techniques are proposed as a method of solving a problem of a capacitor mismatch in a successive approximation A/D converter. The self-calibration techniques add a self-calibration circuit including a capacitor DAC to carry out individual calibration after manufacturing (refer to Non-Patent Document 1, for example).
Using the self-calibration techniques eases an influence of the mismatch of capacitive elements to some extent. However, as for the capacitor DAC included in a self-calibration circuit, the larger a mismatch is, the more a circuit scale increases, which causes a circuit area and a manufacturing cost to increase. Accordingly, it remains preferable to have a lower mismatch of capacitive elements.
Moreover, hitherto, a method is proposed by which a capacitor DAC is made to be a differential structure in order to ease an influence of the voltage dependence of a capacitive element, and the voltages applied to the capacitor DAC on positive side and negative side is made to be the same voltage at a step of sampling and a step of comparing (refer to Patent Document 1, for example).
By employing the above-mentioned constitution, it is possible to cancel a first-order term of the voltage dependence of a capacitive element, and to improve the linearity of an A/D conversion. However, since the terms equal to or higher than second order of the voltage dependence of a capacitive element still remain, the linearity of an A/D conversion receives an influence.
[About Delta-Sigma A/D Converter]
Next, a delta-sigma A/D converter will be illustrated. A delta-sigma A/D converter includes a delta sigma modulator and a digital circuit which performs signal processing.
The delta sigma modulator performs a delta-sigma modulation on an input signal, and transfers a digital signal to a latter digital circuit. The digital circuit extracts desired information from a delta-sigma modulated digital signal, and outputs the information as an A/D conversion result.
A typical delta sigma modulator is realized by a switched capacitor, and includes a sampling circuit, an adding and subtracting circuit, an integrating circuit, and a capacitor DAC. To these components, capacitive elements, such as sampling capacitors, reference capacitors, and integral capacitors, are applied (refer to Non-Patent Document 2, for example).
By the way, in a delta-sigma A/D converter with a 1-bit capacitor DAC, the capacitor DAC only outputs a binary, and therefore, the mismatch of capacitive elements does not directly affect linearity.
However, the mismatch between a sampling capacitor and a reference capacitor affects the offset, and in addition, a mismatch among three capacitances of a sampling capacitor, a reference capacitor, and an integral capacitor affects a gain error. In other words, in order to make the offset and the gain error small, it is desirable to increase the relative accuracy of a capacitive element.
In a delta-sigma A/D converter, the voltage dependence of a capacitance value of a capacitive element affects the linearity of an A/D conversion. It is difficult for a delta-sigma A/D converter which includes a typical structure to make voltage applied to a capacitive element the same voltage at a step of sampling and a step of integrating.
Therefore, a delta-sigma A/D converter requires a capacitive element with even lower voltage dependence in comparison with a successive approximation A/D converter with similar degree of resolution.
In this way, it can be understood that the accuracy of an A/D converter highly depends on the characteristics of a capacitive element, as for a successive approximation A/D converter or a delta-sigma A/D converter.
[About Capacitive Element in Integrated Circuit]
There are a parallel plate structure and a comb-shaped structure as structures of a capacitive element used for an A/D converter with relatively high resolution. The electric field between electrodes seen from a wafer cross-section is a lengthwise direction for the parallel plate structure, and a horizontal direction for the comb-shaped structure.
As capacitive elements for the parallel plate structure, PIP (Poly Insulator Poly), MIM (Metal Insulator Metal), and a structure in which wiring layers are arranged in a comb shape are known. The PIP capacitor is the one which has the parallel plate structure and uses polysilicon for an upper electrode and a lower electrode (refer to Patent Document 2, for example).
In an electrode of the PIP capacitor, a high-concentration semiconductor part which is not an ideal conductor remains even though the surface may be silicidated. Therefore, when a potential difference occurs between terminals, a surface potential of the electrode changes slightly.
In a typical manufacturing process, about 50 ppm/v of the first-order voltage coefficient of a capacitance remains, for example. Therefore, when it is applied to the A/D converter with high resolution, linearity may be damaged and there is a possibility to generate a distortion in the conversion result.
Further, since the PIP capacitor is formed of two-layer polysilicon, there is a problem that a manufacturing cost increases. In other words, a typical MOS process uses at least one layer of polysilicon for gate formation of a transistor, but one more layer of polysilicon is to be used only for forming a capacitive element is added, which causes the increase in a manufacturing cost.
On the other hand, a MIM capacitor has a parallel plate structure and has a structure using metal, such as aluminum, for an upper electrode and a lower electrode. As for the MIM capacitor, since the electrode is metal, there is an advantage that the voltage dependence is even smaller than the PIP capacitor, and generally, the capacitance to ground of a lower electrode is small in comparison with the PIP capacitor.
The MIM capacitor can be classified roughly into two kinds, one including the manufacturing process for forming the MIM capacitor, and the other diverting wiring layers. A manufacturing cost increases due to an additional manufacturing process in the former case, whereas an additional cost does not arise in the latter case since it is possible to form the MIM capacitor simultaneously with wiring (refer to Patent Documents 3 and 4, for example).
These capacitive elements having a parallel plate structure is widely used, when wiring material of an integrated circuit is aluminum.
In addition to above-mentioned capacitor structure, there is one of which wiring layer has a comb-shaped structure. In the recent CMOS manufacturing process, miniaturization of elements progresses and copper is used for a wiring material in many cases. The copper wiring has an advantage of lower interconnection resistance in comparison with aluminum interconnection and has high tolerance for an electromigration.
However, since the copper wiring uses a manufacturing process called a damascene, there is a fault that uniform formation becomes difficult when wiring with narrow width and wiring with wide width are mixed. Since a manufacturing process is optimized according to a copper wiring having minimum width, it is difficult to realize a parallel plate capacitance with a relatively large area. Therefore, when wiring material is copper, a comb-shaped structure is usually employed.
In the old days, a wiring pitch of an integrated circuit is large, and it was not realistic to use a horizontal-direction capacitive coupling as a capacitive element using an wiring layer since it causes an increase of an area of silicon.
However, miniaturization of an integrated circuit device has progressed over time, and a wiring pitch has been shrunk. As a result, capacitors with comb-shaped structure have come to be used widely (refer to Patent Documents 5 and 6, and Non-Patent Documents 3 and 4, for example).
Hitherto, a technique has been also proposed by which a planar shield electrode is provided in each of the uppermost layer and the undermost layer of wiring layers which form capacitors, and an electric field between the electrodes of a capacitive element is shielded, thereby preventing the capacitive coupling which is not intended (refer to Patent Documents 7 and 8, for example).
Hitherto, a technique has been also proposed by which wiring electrically connected to a terminal to which high power source potential is applied and wiring electrically connected to a terminal to which low power source potential is applied are formed so that both wirings are adjacent to each other through dielectric and surround an integrated circuit (refer to Patent Document 9, for example).
As mentioned above, it is preferred that the capacitive element to be applied to the A/D converters, such as the successive approximation A/D converter and the delta-sigma A/D converter, has sufficient relative precision and low voltage dependence to achieve a desired resolution. In order to achieve these requirements, any of a PIP capacitor, an MIM capacitor and a comb-shaped capacitor is used.
Among the capacitive elements, the PIP capacitor has a problem of not being able to be formed by a standard logic manufacturing process, requiring additional manufacturing steps, which increases a manufacturing cost. As for the MIM capacitor with parallel plate structure, there is a possibility to reduce a cost by forming electrodes simultaneously with an interconnecting process.
However, a parallel plate structure can be employed only when wiring material is aluminum, and it is difficult to form the structure by a copper wiring process. In other words, a comb-shaped capacitor is usually adopted in a copper wiring process in order to make a high resolution A/D converter without an additional manufacturing process. However, there are various problems in a comb-shaped capacitor as illustrated in detail below.
Patent Document 1: Japanese Laid-open Patent Publication No. 2007-142863
Patent Document 2: U.S. Pat. No. 4,914,546
Patent Document 3: U.S. Pat. No. 5,220,483
Patent Document 4: U.S. Pat. No. 6,066,537
Patent Document 5: U.S. Pat. No. 5,583,359
Patent Document 6: Japanese Laid-open Patent Publication No. 2005-108874
Patent Document 7: U.S. Pat. No. 6,737,698
Patent Document 8: Japanese Laid-open Patent Publication No. 2005-197396
Patent Document 9: Japanese Laid-open Patent Publication No. 2009-278078
Non-Patent Document 1: H. S. Lee et al., “A Self-Calibrating 15 Bit CMOS A/D Converter,” IEEE Journal of Solid-State Circuits Vol. SC-19, No. 6, December 1984
Non-Patent Document 2: B. E. Boser et al., “The deisgn of sigma-delta modulation analog-to-digital converters,” IEEE Journal of Solid-State Circuits, Vol. 23, pp. 1298-1308, December 1988
Non-Patent Document 3: K. T. Christensen, “Design and characterization of vertical mesh capacitors in standard CMOS,” Symp. VLSI Technol., pp. 201-204, 2001
Non-Patent Document 4: Aparicio et al., “Capacity limits and matching properties of integrated capacitors,” IEEE J. Solid-State Circuits, vol. 37, pp. 384-393, 2002